Design and security evaluation of balanced 1-of-n circuits

A new balanced library is presented which consists of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Cryptographic circuit specifications are refined and passed to optimization and mapping tools for mapping to a library of power-balanced components. Logic optimization tools are then applied to generate secure synchronous circuits for layout generation. This paper presents a new technique for evaluating the security of such circuits in particular those which offer a higher level of protection. A security metric is introduced which is based on the common selection function that is widely used in DPA attacks and a correlation measure similar to the one used in CPA attacks. This is used to compare the security level for these kinds of balanced circuits that are more difficult to attack. The paper shows that the circuits generated are more efficient and can offer a higher level of security than those generated by alternative techniques.